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CY22050, CY220501
One-PLL General Purpose Flash Programmable Clock Generator
Features

Benefits
Integrated phase-locked loop (PLL) Commercial and Industrial operation Flash-programmable Field-programmable Low-skew, low-jitter, high-accuracy outputs 3.3V operation with 2.5V output option 16-Pin TSSOP package (CY22050) 16-Pin TSSOP package with NiPdAu lead finish (CY220501)
Internal PLL to generate six outputs up to 200 MHz. Able to generate custom frequencies from an external reference crystal or driven source. Performance guaranteed for applications that require an extended temperature range. Reprogrammable technology allows easy customization, quick turnaround on design changes and product performance enhancements, and better inventory control. Parts can be reprogrammed up to 100 times, reducing inventory of custom parts and providing an easy method for upgrading existing designs. In-house programming of samples and prototype quantities is available using the CY3672 FTG Development Kit. Production quantities are available through Cypress's value-added distribution partners or by using third party programmers from BP Microsystems, HiLo Systems, and others. Industry standard packaging saves on board space. Output Frequency Range Specifications Field-programmable commercial temperature Field-programmable industrial temperature Field-programmable industrial temperature NiPdAu lead finish

Table 1. Device Selection Part Number CY22050KFZXC CY22050KFZXI CY220501KFZXI Outputs 6 6 6 Input Frequency Range 8 MHz-30 MHz (external crystal) 1 MHz-133 MHz (driven clock) 8 MHz-30 MHz (external crystal) 1 MHz-133 MHz (driven clock) 8 MHz-30 MHz (external crystal) 1 MHz-133 MHz (driven clock) 80 kHz-200 MHz (3.3V) 80 KHz-166.6 MHz (2.5V) 80 kHz-166.6 MHz (3.3V) 80 KHz-150 MHz (2.5V) 80 kHz-166.6 MHz (3.3V) 80 KHz-150 MHz (2.5V)
Logic Block Diagram
LCLK1 Divider Bank 1 Output Select Matrix VCO P PLL Divider Bank 2 CLK5 CLK6 LCLK2 LCLK3 LCLK4
XIN XOUT
OSC.
Q
OE VDD AVDD AVSS VSS VDDL VSSL PWRDWN
Cypress Semiconductor Corporation Document #: 38-07006 Rev. *G
*
198 Champion Court
*
San Jose, CA 95134-1709
* 408-943-2600 Revised July 24, 2009
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CY22050, CY220501
Pin Configuration
Figure 1. 16-Pin TSSOP
XIN VDD AVDD PWRDWN AVSS VSSL LCLK1 LCLK2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 XOUT CLK6 CLK5 VSS LCLK4 VDDL OE LCLK3
Table 2. Pin Definitions Name XIN Pin Number 1 Description Reference Input. Driven by a crystal (8 MHz-30 MHz) or external clock (1 MHz-133 MHz). Programmable input load capacitors allow for maximum flexibility in selecting a crystal, based on manufacturer, process, performance, or quality. 3.3V voltage supply 3.3V analog voltage supply Power Down. When pin 4 is driven LOW, the CY22050 goes into shut down mode. Analog ground LCLK ground Configurable clock output 1 at VDDL level (3.3V or 2.5V) Configurable clock output 2 at VDDL level (3.3V or 2.5V) Configurable clock output 3 at VDDL level (3.3V or 2.5V) Output Enable. When pin 10 is driven LOW, all outputs are three-stated. LCLK voltage supply (2.5V or 3.3V) Configurable clock output 4 at VDDL level (3.3V or 2.5V) Ground Configurable clock output 5 (3.3V) Configurable clock output 6 (3.3V) Reference output
VDD AVDD PWRDWN[1] AVSS VSSL LCLK1 LCLK2 LCLK3 OE[1] VDDL LCLK4 VSS CLK5 CLK6 XOUT[2]
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Notes 1. The CY22050 has no internal pull up or pull down resistors. PWRDWN and OE pins need to be driven as appropriate or tied to power or ground. 2. Float XOUT if XIN is driven by an external clock source.
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CY22050, CY220501
Functional Description
The CY22050 is the next-generation programmable FTG (frequency timing generator) for use in networking, telecommunication, datacom, and other general-purpose applications. The CY22050 offers up to six configurable outputs in a 16-pin TSSOP, running off a 3.3V power supply. The on-chip reference oscillator is designed to run off an 8-30-MHz crystal, or a 1-133-MHz external clock signal. The CY22050 has a single PLL driving 6 programmable output clocks. The output clocks are derived from the PLL or the reference frequency (REF). Output post dividers are available for either. Four of the outputs can be set as 3.3V or 2.5V, for use in a wide variety of portable and low-power applications. The CY220501 is the CY22050 with NiPdAu lead finish.
Applications
Controlling Jitter
Jitter is defined in many ways, including: phase noise, long-term jitter, cycle-to-cycle jitter, period jitter, absolute jitter, and deterministic jitter. These jitter terms are usually given in terms of rms, peak-to-peak, or in the case of phase noise dBC/Hz with respect to the fundamental frequency. Actual jitter is dependent on XIN jitter and edge rate, number of active outputs, output frequencies, VDDL (2.5V or 3.3V), temperature, and output load. Power supply noise and clock output loading are two major system sources of clock jitter. Power supply noise can be mitigated by proper power supply decoupling (0.1-F ceramic cap) of the clock and ensuring a low-impedance ground to the chip. Reducing capacitive clock output loading to a minimum lowers current spikes on the clock edges and thus reduces jitter. Reducing the total number of active outputs also reduce jitter in a linear fashion. However, it is better to use two outputs to drive two loads than one output to drive two loads. The rate and magnitude that the PLL corrects the VCO frequency is directly related to jitter performance. If the rate is too slow, then long term jitter and phase noise is poor. Therefore, to improve long-term jitter and phase noise, reducing Q to a minimum is advisable. This technique increases the speed of the phase frequency detector, which in turn drives the input voltage of the VCO. In a similar manner, increasing P until the VCO is near its maximum rated speed also decreases long term jitter and phase noise. For example: input reference of 12 MHz; desired output frequency of 33.3 MHz. One might arrive at the following solution: Set Q = 3, P = 25, Post Div = 3. However, the best jitter results are Q = 2, P = 50, Post Div = 9. For additional information, refer to the application note, "Jitter in PLL-based Systems: Causes, Effects, and Solutions," available at http://www.cypress.com (click on "Application Notes"), or contact your local Cypress Field Applications Engineer.
Field Programming the CY22050F
The CY22050 is programmed at the package level, that is, in a programmer socket, prior to installation on a PCB. The CY22050 is flash-technology based, so the parts can be reprogrammed up to 100 times. This allows for fast and easy design changes and product updates, and eliminates any issues with old and out-of-date inventory. Samples and small prototype quantities can be programmed on the CY3672 programmer. Cypress's value-added distribution partners and third-party programming systems from BP Microsystems, HiLo Systems, and others are available for large-production quantities.
CyberClocksTM Software
CyberClocks is an easy-to-use software application that allows the user to custom-configure the CY22050. Within CyberClocks, select the CyClocksRTTM tool. Users can specify the REF, PLL frequency, output frequencies and/or post-dividers, and different functional options. CyClocksRT outputs an industry-standard JEDEC file used for programming the CY22050. CyClocksRT can be downloaded free of charge from the Cypress website at http://www.cypress.com. Install and run it on any PC running the Windows operating system.
CY3672 Development Kit
The Cypress CY3672 Development Kit comes complete with everything needed to design with the CY22050 and program samples and small prototype quantities. The kit comes with the latest version of CyClocksRT and a small portable programmer that connects to a PC for on-the-fly programming of custom frequencies. The JEDEC file output of CyClocksRT can be downloaded to the portable programmer for small-volume programming, or for use with a production programming system for larger volumes.
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CY22050, CY220501
CY22050 Frequency Calculation
The CY22050 is an extremely flexible clock generator with up to six individual outputs, generated from an integrated PLL. There are four variables used to determine the final output frequency. They are: the input REF, the P and Q dividers, and the post divider. The three basic formulas for determining the final output frequency of a CY22150-based design are:

and can be independent of each other. The post divider options can be applied to the calculated PLL frequency or to the REF directly. In addition to the six post divider options, the seventh option bypasses the PLL and passes the REF directly to the crosspoint switch matrix.
CLK = ((REF * P)/Q)/Post Divider CLK = REF/Post Divider CLK = REF
Clock Output Settings: Crosspoint Switch Matrix
Each of the six clock outputs can come from any of seven unique frequency sources. The crosspoint switch matrix defines which source is attached to each individual clock output. Although it may seem that there are an unlimited number of divider options, there are several rules that must be taken into account when selecting divider options.
The basic PLL block diagram is shown in Figure 2. Each of the six clock outputs has a total of seven output options available to it. There are six post divider options: /2 (two of these), /3, /4, /DIV1N, and DIV2N. DIV1N and DIV2N are separately calculated
Figure 2. Basic PLL Block Diagram
Divider Bank 1
/DIV1N
LCLK1 LCLK2 LCLK3
Crosspoint Switch Matrix
REF
Q
PFD P
VCO
/2
/3
Divider Bank 2
LCLK4 CLK5 CLK6
/4 /2
/DIV2N
Table 3. Clock Output Definition Clock Output Divider None /DIV1N /2 /3 /DIV2N /2 /4 Definition and Notes Clock output source is the reference input frequency Clock output uses a generated /DIV1N option from Divider Bank 1. Allowable values for DIV1N are 4 to 127. If Divider Bank 1 is not being used, set DIV1N to 8. Clock output uses a fixed /2 option from Divider Bank 1. If this option is used, DIV1N must be divisible by 4. Clock output uses a fixed /3 option from Divider Bank 1. If this option is used, set DIV1N to 6. Clock output uses a generated /DIV2N option from Divider Bank 2. Allowable values for DIV2N are 4 to 127. If Divider Bank 2 is not being used, set DIV2N to 8. Clock output uses a fixed /2 option from Divider Bank 2. If this option is used, DIV2N must be divisible by 4. Clock output 2 uses a fixed /4 option from Divider Bank 2. If this option is used, DIV2N must be divisible by 8.
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CY22050, CY220501
Reference Crystal Input
The input crystal oscillator of the CY22050 is an important feature because of the flexibility it allows the user in selecting a crystal as a reference clock source. The oscillator inverter has programmable gain, allowing for maximum compatibility with a reference crystal, based on manufacturer, process, performance, and quality. The value of the input load capacitors is determined by eight bits in a programmable register. Total load capacitance is determined by the formula: CapLoad = (CL - CBRD - CCHIP)/0.09375 pF
In CyClocksRT, enter the crystal capacitance (CL). The value of CapLoad is determined automatically and programmed into the CY22050. If you require greater control over the CapLoad value, consider using the CY22150 for serial configuration and control of the input load capacitors. For an external clock source, the default is 0. Input load capacitors are placed on the CY22050 die to reduce external component cost. These capacitors are true parallel-plate capacitors, designed to reduce the frequency shift that occurs when non-linear load capacitance is affected by load, bias, supply, and temperature changes.
Absolute Maximum Conditions
Parameter VDD VDDL TS TJ Supply Voltage I/O Supply Voltage Storage Temperature[3] Junction Temperature Package Power Dissipation--Commercial Temp Package Power Dissipation--Industrial Temp Digital Inputs Digital Outputs referred to VDD Digital Outputs referred to VDDL ESD Static Discharge Voltage per MIL-STD-833, Method 3015 AVSS - 0.3 VSS - 0.3 VSS - 0.3 Description Min -0.5 -0.5 -65 Max 7.0 7.0 125 125 450 380 AVDD + 0.3 VDD + 0.3 VDDL +0.3 2000 Unit V V C C mW mW V V V V
Recommended Operating Conditions
Parameter VDD VDDLHI VDDLLO TAC TAI CLOAD CLOAD fREFD fREFC tPU Operating Voltage Operating Voltage Operating Voltage Ambient Commercial Temp Ambient Industrial Temp Max. Load Capacitance VDD/VDDL = 3.3V Max. Load Capacitance VDDL = 2.5V Driven REF Crystal REF Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 1 8 0.05 Description Min 3.135 3.135 2.375 0 -40 Typ. 3.3 3.3 2.5 Max 3.465 3.465 2.625 70 85 15 15 133 30 500 Unit V V V C C pF pF MHz MHz ms
Note 3. Rated for 10 years
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DC Electrical Characteristics
Parameter[4] IOH3.3 IOL3.3 IOH2.5 IOL2.5 VIH VIL IVDD[5,6] IVDDL3.3[5,6] IVDDL2.5[5,6] IDDS IOHZ IOLZ Name Output High Current Output Low Current Output High Current Output Low Current Input High Voltage Input Low Voltage Supply Current Supply Current Supply Current Power Down Current Output Leakage Description VOH = VDD - 0.5V, VDD/VDDL = 3.3V VOL = 0.5V, VDD/VDDL = 3.3V VOH = VDDL - 0.5V, VDDL = 2.5V VOL = 0.5V, VDDL = 2.5V CMOS levels, 70% of VDD CMOS levels, 30% of VDD AVDD/VDD Current VDDL Current (VDDL = 3.465V) VDDL Current (VDDL = 2.625V) VDD = VDDL = AVDD = 3.465V VDD = VDDL = AVDD = 3.465V Min 12 12 8 8 0.7 0 45 25 17 50 10 Typ. 24 24 16 16 1.0 0.3 Max Unit mA mA mA mA VDD VDD mA mA mA A A
AC Electrical Characteristics
Parameter[4] t1 Name Output frequency, commercial temp Description Clock output limit, 3.3V Clock output limit, 2.5V Min 0.08 (80 kHz) 0.08 (80 kHz) 0.08 (80 kHz) 0.08 (80 kHz) 40 45 0.6 0.6 0.8 0.8 50 50 1.2 1.2 1.4 1.4 250 250 0.30 3 Typ. Max 200 166.6 166.6 150 60 55 Unit MHz MHz MHz MHz % % V/ns V/ns V/ns V/ns ps ps ms
Output frequency, indus- Clock output limit, 3.3V trial temp Clock output limit, 2.5V t2 Output duty cycle Duty cycle is defined in Figure 4; t1/t2 fOUT > 166 MHz, 50% of VDD Duty cycle is defined in Figure 4; t1/t2 fOUT < 166 MHz, 50% of VDD t3LO t4LO t3HI t4HI t5[7] t6[8] t10 Rising edge slew rate (VDDL = 2.5V) Falling edge slew rate (VDDL = 2.5V) Rising edge slew rate (VDDL = 3.3V) Falling edge slew rate (VDDL = 3.3V) Skew Clock jitter PLL lock time Output clock rise time, 20% - 80% of VDDL. Defined in Figure 5 Output clock fall time, 80% - 20% of VDDL. Defined in Figure 5 Output clock rise time, 20% - 80% of VDD/VDDL. Defined in Figure 5 Output clock fall time, 80% - 20% of VDD/VDDL. Defined in Figure 5 Output-output skew between related outputs Peak-to-peak period jitter (see Figure 6)
Notes 4. Not 100% tested, guaranteed by design. 5. IVDD currents specified for two CLK outputs running at 125 MHz, two LCLK outputs running at 80 MHz, and two LCLK outputs running at 66.6 MHz. All outputs are loaded with 15pF. 6. Use CyClocksRT to calculate actual IVDD and IVDDL for specific output frequency configurations. 7. Skew value guaranteed when outputs are generated from the same divider bank. See Logic Block Diagram for more information. 8. Jitter measurement will vary. Actual jitter is dependent on XIN jitter and edge rate, number of active outputs, output frequencies, VDDL (2.5V or 3.3V), temperature, and output load. For more information, refer to the application note, "Jitter in PLL-based Systems: Causes, Effects, and Solutions," available at http://www.cypress.com, or contact your local Cypress Field Applications Engineer.
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Figure 3. Test Circuit
VDD 0.1 F OUTPUTS
CLK out CLOAD
AVDD 0.1 F GND
Figure 4. Duty Cycle Definition: DC = t2/t1
VDDL 0.1 F
t1 t2
CLK
50%
50%
Figure 5. Rise and Fall Time Definitions
t3 80% t4
CLK
20%
Figure 6. Peak-to-Peak Jitter
t6
CLK
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CY22050, CY220501
Ordering Information
Ordering Code CY22050FC[9] CY22050FI[9] CY22050ZC-xxx[9, 10] CY22050KFC CY22050KFI Pb-Free CY220501KFZXI CY22050FZXC[9] CY22050FZXI[9] CY22050ZXC-xxx[9, 10] CY22050ZXC-xxxT[9, 10] CY22050ZXI-xxx[9, 10] CY22050ZXI-xxxT[9, 10] CY22050KFZXC CY22050KFZXI CY22050KZXC-xxx[10] CY22050KZXC-xxxT[10] CY22050KZXI-xxx[10] CY22050KZXI-xxxT[10] Programmer CY3672-USB CY3695 Programming Kit CY22050F, CY22050KFand CY220501KF Adapter for CY3672 Programmer 16-lead TSSOP with NiPdAu lead finish 16-lead TSSOP 16-lead TSSOP 16-lead TSSOP 16-lead TSSOP-Tape and Reel 16-lead TSSOP 16-lead TSSOP-Tape and Reel 16-lead TSSOP 16-lead TSSOP 16-lead TSSOP 16-lead TSSOP-Tape and Reel 16-lead TSSOP 16-lead TSSOP-Tape and Reel Industrial (-40 to 85C) Commercial (0 to 70C) Industrial (-40 to 85C) Commercial (0 to 70C) Commercial (0 to 70C) Industrial (-40 to 85C) Industrial (-40 to 85C) Commercial (0 to 70C) Industrial (-40 to 85C) Commercial (0 to 70C) Commercial (0 to 70C) Industrial (-40 to 85C) Industrial (-40 to 85C) 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 16-lead TSSOP 16-lead TSSOP 16-lead TSSOP 16-lead TSSOP 16-lead TSSOP Package Type Temperature Operating Range Commercial (0 to 70C) Industrial (-40 to 85C) Commercial (0 to 70C) Commercial (0 to 70C) Industrial (-40 to 85C) Operating Voltage 3.3V 3.3V 3.3V 3.3V 3.3V
16-Pin TSSOP Package Characteristics
Parameter JA Complexity Name theta JA Transistor Count Value 115 74,600 Unit C/W Transistors
Notes 9. Not recommended for new designs. Part numbers without a "K" are being replaced by part numbers with a "K". There are no changes to device specifications as a result of the part number change. 10. The CY22050KZXC-xxx and CY22050KZXI-xxx are factory-programmed configurations. Factory programming is available for high-volume design opportunities of 100 Ku/year or more in production. For more details, contact your local Cypress field application engineer or Cypress sales representative.
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Package Drawing and Dimensions
Figure 7. 16-Pin TSSOP 4.40 MM Body Z16.173
PIN 1 ID
1
DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153
6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177]
PACKAGE WEIGHT 0.05gms
16
0.65[0.025] BSC.
0.19[0.007] 0.30[0.012]
1.10[0.043] MAX.
0.25[0.010] BSC GAUGE PLANE 0-8
0.076[0.003] 0.85[0.033] 0.95[0.037] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008]
4.90[0.193] 5.10[0.200]
51-85091-*A
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Document History Page
Document Title: CY22050, CY220501 One-PLL General Purpose Flash-Programmable Clock Generator Document Number: 38-07006 REV. ** *A *B *C *D *E ECN 108185 110054 121862 310575 314233 2440826 Orig. of Change CKN CKN RBI RGL RGL AESA Submission Date 08/08/01 03/04/02 12/14/02 01/20/05 01/31/05 05/15/08 New Data Sheet. Changed from Preliminary to Final. Power up requirements added to Operating Conditions Information. Added Lead-free devices. Removed the Tape and Reel devices in the non-dash parts. Updated template. Added Note "Not recommended for new designs." and "38-07409, CY3672 PTG Programming Kit". Corrected "FTG" to PTG" in Ordering information table. Added part numbers CY22050KFC, CY22050KFI, CY22050KFZXC, CY22050KFZXI, CY22050KZXC-xxx, CY22050KZXC-xxxT, CY22050KZXI-xxx, and CY22050KZXI-xxxT in ordering information table. Changed Lead-Free to Pb-Free. Added CY220501 to title. Added CY220501KFZXI to ordering table. Revised the Device Selection table on page 1 and renamed it. Updates to programmer and softwre descriptions. Clarified that IVDD and IVDDL are for loaded outputs. Updated footnotes to show that the standard part numbers are now with a "K". Changed CY3672 part number to CY3672-USB, changed CY3672ADP000 to CY3695, and repositioned them in the Ordering Information table. Deleted part numbers CY22050ZC-xxxT, CY22050ZI-xxx and CY22050ZI-xxxT. Description of Change
*F *G
2642064 2743347
KVM KVM
01/21/09 07/24/09
Sales, Solutions, and Legal Information
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(c) Cypress Semiconductor Corporation, 2001-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07006 Rev. *G
Revised July 24, 2009
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BP Microsystems is a trademark of BP Microsystems. Hilo Systems is a trademark of Hi-Lo Systems. All product and company names mentioned in this document are the trademarks of their respective holders.
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